1. Field of the Invention
The present invention relates to an arrangement of controlling memory access requests to a plurality of memory banks in a digital data processing system, and more specifically to such an arrangement in which the memory banks to be accessed, are arranged in interleaved groups. The present invention features effective reduction of the number of read/write data control registers which are inherently required to be coupled to the banks.
2. Description of the Prior Art
In order to obtain a higher data rate in storing information into a memory and retrieving same therefrom, it is known to utilizing an approach called interleaving. The interleaved groups of memory chips are referred to as banks.
When data is to be memorized, data set-up time and data hold time are required to assuredly store and retrieve the data. Accordingly, in accordance with prior art techniques, a pair of read and write data control registers (hereinafter referred to as "data control registers") are provided for each bank.
In order to reduce the number of components in a digital data processing system, it is very desirable if all of the data control registers to be provided for the banks can be configured on a single LSI (Large Scale Integration) chip. However, in accordance with the prior art techniques, since each bank requires two data control registers for read and write operations, the number of pins of the LSI chip increases with increase in the number of data control registers fabricated therein. The number of pins of such a LSI chip is determined by multiplying the data width two times the number of data control registers to be provided.
The prior art techniques therefore have encountered the problem in that the data control registers to be used cannot be accommodated in one LSI chip in the event that the number of data control registers increases. This of course creates a barrier which must be overcome before the degree of integration can be overcome.